{"created":"2023-06-19T10:35:14.409861+00:00","id":1189,"links":{},"metadata":{"_buckets":{"deposit":"f77c6057-9767-49cb-bff0-e9e07c2f02ea"},"_deposit":{"created_by":14,"id":"1189","owners":[14],"pid":{"revision_id":0,"type":"depid","value":"1189"},"status":"published"},"_oai":{"id":"oai:ous.repo.nii.ac.jp:00001189","sets":["296:314:330"]},"author_link":[],"item_1_biblio_info_14":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1997-03-31","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"102","bibliographicPageStart":"93","bibliographicVolumeNumber":"32","bibliographic_titles":[{"bibliographic_title":"岡山理科大学紀要. A, 自然科学","bibliographic_titleLang":"ja"},{"bibliographic_title":"Bulletin of Okayama University of Science. A, Natural Sciences","bibliographic_titleLang":"en"}]}]},"item_1_creator_6":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"天谷, 純治","creatorNameLang":"ja"},{"creatorName":"アマヤ, ジュンジ","creatorNameLang":"ja-Kana"},{"creatorName":"Amaya, Junji","creatorNameLang":"en"}]},{"creatorNames":[{"creatorName":"多田, 昭晴","creatorNameLang":"ja"},{"creatorName":"タダ, アキハル","creatorNameLang":"ja-Kana"},{"creatorName":"Tada, Akiharu","creatorNameLang":"en"}]}]},"item_1_description_1":{"attribute_name":"ページ属性","attribute_value_mlt":[{"subitem_description":"P(論文)","subitem_description_type":"Other"}]},"item_1_description_12":{"attribute_name":"抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, LSI technology have been progressed to be widly use. Systems are highly complex and LSI have over a million elements. Inspection of its function becomes very difficult. And the costs of LSI design such as Application Specific Integrated Circuit (ASIC) became higher cause of various kinds and small quantity production. Rapidly LSI design and low costs method of LSI design have been required. Hardware Descripsion Language (HDL) solves these probrems. In LSI design, HDL method provides high quality with computer-aided design tools. Verilog-HDL is one of a HDL provides the system designer with a wide range of levels of abstruction, and, at the same time, provides access to computer-aided design tools to aid in the design process at these levels. This paper describes process of synthesis for 8 channel Pulse Width Modulation circuit with verilog-HDL.","subitem_description_language":"en","subitem_description_type":"Other"}]},"item_1_source_id_13":{"attribute_name":"雑誌書誌ID","attribute_value_mlt":[{"subitem_source_identifier":"AN00033244","subitem_source_identifier_type":"NCID"}]},"item_1_text_10":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_language":"en","subitem_text_value":"Graduate School of Engineering, Okayama University of Science"},{"subitem_text_language":"en","subitem_text_value":"Department of Information and Computer Engineering, Okayama University of Science"}]},"item_1_text_9":{"attribute_name":"著者所属(日)","attribute_value_mlt":[{"subitem_text_language":"ja","subitem_text_value":"岡山理科大学大学院工学研究科修士課程情報工学専攻"},{"subitem_text_language":"ja","subitem_text_value":"岡山理科大学工学部情報工学科"}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"1997-03-31"}],"displaytype":"detail","filename":"KJ00000063698.pdf","filesize":[{"value":"369.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"url":"https://ous.repo.nii.ac.jp/record/1189/files/KJ00000063698.pdf"},"version_id":"6a0f7869-cdae-40a0-a916-80fe93f58a50"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Verilog-HDLによる8chPWM回路の論理合成","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Verilog-HDLによる8chPWM回路の論理合成","subitem_title_language":"ja"},{"subitem_title":"Logic Synthesis for 8 channel Pulse Width Modulation with Verilog-HDL","subitem_title_language":"en"},{"subitem_title":"Verilog-HDL ニヨル 8ch PWM カイロ ノ ロンリ ゴウセイ","subitem_title_language":"ja-Kana"}]},"item_type_id":"1","owner":"14","path":["330"],"pubdate":{"attribute_name":"PubDate","attribute_value":"1997-03-31"},"publish_date":"1997-03-31","publish_status":"0","recid":"1189","relation_version_is_last":true,"title":["Verilog-HDLによる8chPWM回路の論理合成"],"weko_creator_id":"14","weko_shared_id":-1},"updated":"2023-09-28T00:55:22.537898+00:00"}