@article{oai:ous.repo.nii.ac.jp:00001189,
 author = {天谷, 純治 and Amaya, Junji and 多田, 昭晴 and Tada, Akiharu},
 journal = {岡山理科大学紀要. A, 自然科学, Bulletin of Okayama University of Science. A, Natural Sciences},
 month = {Mar},
 note = {P(論文), Recently, LSI technology have been progressed to be widly use. Systems are highly complex and LSI have over a million elements. Inspection of its function becomes very difficult. And the costs of LSI design such as Application Specific Integrated Circuit (ASIC) became higher cause of various kinds and small quantity production. Rapidly LSI design and low costs method of LSI design have been required. Hardware Descripsion Language (HDL) solves these probrems. In LSI design, HDL method provides high quality with computer-aided design tools. Verilog-HDL is one of a HDL provides the system designer with a wide range of levels of abstruction, and, at the same time, provides access to computer-aided design tools to aid in the design process at these levels. This paper describes process of synthesis for 8 channel Pulse Width Modulation circuit with verilog-HDL.},
 pages = {93--102},
 title = {Verilog-HDLによる8chPWM回路の論理合成},
 volume = {32},
 year = {1997},
 yomi = {アマヤ, ジュンジ and タダ, アキハル}
}